A liquid crystal display device of the multi-pixel drive method offers improved gamma characteristics dependence on view angle. In the multi-pixel drive, a single pixel is composed of two or more subpixels having different levels of brightness for improved view angle characteristics, that is, gamma characteristics dependence on view angle.
FIG. 7 shows a structural example of a pixel in such a liquid crystal display device of the multi-pixel drive method (see Patent Document 1, for example).
One pixel P is divided into two subpixels, sp1 and sp2. The subpixel sp1 includes a TFT 16a, a subpixel electrode 18a, and an auxiliary capacitance 22a, while the subpixel sp2 includes a TFT 16b, a subpixel electrode 18b, and an auxiliary capacitance 22b. 
Gate electrodes of the TFT 16a and TFT 16b are connected to a mutually common gate bus line GL, and source electrodes are connected to a mutually common source bus line SL. The auxiliary capacitance 22a is formed between the subpixel electrode 18a and an auxiliary capacitance bus line CsL1, while the auxiliary capacitance 22b is formed between the subpixel electrode 18b and an auxiliary capacitance bus line CsL2. The auxiliary capacitance bus line CsL1 is formed in such a way as to extend in parallel with the aforementioned gate bus line GL with the region of the subpixel sp1 interposed between itself and the gate bus line GL. The auxiliary capacitance bus line CsL2 is formed in such a way as to extend in parallel with the aforementioned gate bus line GL with the region of the subpixel sp2 interposed between itself and the gate bus line GL.
Furthermore, the auxiliary capacitance bus line CsL1 of a pixel P is also the auxiliary capacitance bus line CsL2, with which the subpixel sp2 of another pixel P, which adjoins the aforementioned pixel P through the aforementioned auxiliary capacitance bus line CsL1, forms the auxiliary capacitance 22b; and the auxiliary capacitance bus line CsL2 of a pixel P is also the auxiliary capacitance bus line CsL1, with which the subpixel sp1 of another pixel P, which adjoins the aforementioned pixel P through the aforementioned auxiliary capacitance bus line CsL2, forms the auxiliary capacitance 22a. 
A method of driving the auxiliary capacitance bus lines CsL1 and CsL2 in the display panel of the multi-pixel drive method will be described below with reference to FIG. 8 and FIG. 9.
As shown in FIG. 8, the auxiliary capacitance bus lines CsL (CsL designation is used, when CsL1 and CsL2 are not distinguished) are placed alternately in an active area AA, which is a display region, and connected to CS trunk wiring lines bb placed in a region adjoining the active area AA. A plurality of the CS trunk wiring lines bb forms a set of CS trunk wiring group BB. Only one set of CS trunk wiring group BB is formed in a region adjoining the active area AA on one end, which is a predetermined side, of the direction in which the auxiliary capacitance bus lines CsL extend, or in other words, only one set is formed in the region on one side. Alternatively, one set of the CS trunk wiring group BB is formed in a region adjoining the active area AA on one side, which is a predetermined side, of the direction in which the auxiliary capacitance bus lines CsL extend, and another set is formed in another region adjoining on the other side, or in other words, one CS trunk wiring group BB each is formed in the regions on both sides.
When the CS trunk wiring group BB is formed only in the region on one side, the ends of the auxiliary capacitance bus lines CsL on the aforementioned predetermined side are connected to the CS trunk wiring lines bb. When the CS trunk wiring groups BB are formed in the regions on both sides, one ends of the auxiliary capacitance bus lines CsL on the aforementioned predetermined side are connected to the CS trunk wiring lines bb in the region adjoining on the aforementioned one side, while the other ends of the auxiliary capacitance bus lines CsL are connected to the CS trunk wiring lines bb in the region adjoining the aforementioned other side. The CS trunk wiring lines bb extend in a direction orthogonal to the direction in which the auxiliary capacitance bus lines CsL1 and CsL2 extend. That is, the CS trunk wiring lines bb extend in the direction in which the source bus line SL extends.
An example is shown in FIG. 8 in which the CS trunk wiring groups BB, which include twelve CS trunk wiring lines bb, are disposed in both regions. Each auxiliary capacitance bus line CsL is connected to a single CS trunk wiring line bb in each CS trunk wiring group BB. The twelve auxiliary capacitance bus lines CsL (the number of CS trunk wiring lines bb constituting a CS trunk wiring group BB is also twelve or n (n is an even number)) are sequentially connected to mutually different CS trunk wiring lines bb in each of the CS trunk wiring groups BB, and the connective relationship is repeated for every twelve (or n) auxiliary capacitance bus lines.
When the CS trunk wiring group BB is formed only in one of the regions, the n number of auxiliary capacitance bus lines CsL, which are laid out sequentially, are connected to mutually different CS trunk wiring lines bb in the aforementioned CS trunk wiring group BB, and the sequential relationship is repeated for every n number of auxiliary capacitance bus lines.
Furthermore, separate auxiliary capacitance voltages, as shown in FIG. 9, are applied on each of n number of auxiliary capacitance bus lines CsL, which are laid out sequentially in both cases where the CS trunk wiring group BB is formed only in the region on one side and where the CS trunk wiring groups BB are formed in the regions on both sides. The auxiliary capacitance voltages Vcs (Vcs1, Vcs2, . . . in the figure) between the auxiliary capacitance bus lines CsL1 and CsL2, which correspond to the subpixels sp1 and sp2 in the same pixel P on the odd numbered lines, form waveforms of binary levels having the same level shift timings and the same periodicity but swing within different ranges. Furthermore, the auxiliary capacitance voltages Vcs, which form pairs, are set up in an n/2 number of pairs having phases which are slightly off among the odd numbered lines. Gate pulses Vg (Vg1, Vg3 . . . in the figure) on the odd numbered lines have a pulse period that lasts for a certain length of time and the timing of the end of the pulse period corresponds to a rising edge or a falling edge of the auxiliary capacitance voltages Vcs.
As a result, data signals are first written into the pixels P on the odd numbered lines; and, with a change in the auxiliary capacitance voltage Vcs after the data signal is written, different potential changes ΔV is added to the voltage levels of the pixel electrodes of the two subpixels sp1 and sp2 of the pixel P, to which the same data signals have been written, because of a feed-through phenomenon via the capacitance between the gate bus line GL and the pixel electrodes. As a result, the aforementioned sub-pixels sp1 and sp2 have different levels of brightness, and the average brightness, derived from an effective value of voltages applied on the liquid crystal throughout a single frame period of the auxiliary capacitance voltages Vcs, provides appropriate gamma characteristics for the entire pixel P within a wide range of view angles.
After a scan on an odd numbered line, a scan on an even numbered line is performed. In such an instance, the auxiliary capacitance voltages Vcs applied on the subpixels sp1 and sp2 belonging to the same pixel P do not form pairs having the same level shift timings as on an odd numbered line but nevertheless improves the gamma characteristics, because the first voltage shift of the pixel electrode after the end of the gate pulse is similar to that of the odd numbered line.
The waveforms and the method of scanning described above for the auxiliary capacitance voltages Vcs are only an example. The main aspect of this technology is the improvement in the gamma characteristics for the entire pixel P, which is achieved by making the brightness different between the subpixels sp1 and sp2 using different voltage shifts in the auxiliary capacitance voltage Vcs.
Since such auxiliary capacitance voltages Vcs are supplied through the CS trunk wiring lines bb, different auxiliary capacitance voltages Vcs are applied on respective CS trunk wiring lines bb in each CS trunk wiring group BB. Therefore, the auxiliary capacitance voltages Vcs having the same number of phases as the number of CS trunk wiring lines bb are supplied from a CS driver (not shown in the figure) to the CS trunk wiring group BB. FIG. 9 shows an example in which the auxiliary capacitance voltages Vcs are supplied in 12 phases. Furthermore, as shown in FIG. 8, when the CS trunk wiring groups BB are placed on both sides of the active area AA, the same auxiliary capacitance voltage Vcs is applied on the CS trunk wiring lines bb in both CS trunk wiring groups BB that are connected to the same auxiliary capacitance bus line CsL. Because an auxiliary capacitance voltage Vcs is supplied from both sides of the active area AA, the waveforms of the auxiliary capacitance voltage Vcs is less likely to be different at different locations in the active area AA in spite of wiring delays across a larger liquid crystal display panel.